1. Field of the Invention
The present invention relates to an ultralow power differential amplifier circuit that uses an adaptive bias current generator circuit.
2. Description of the Related Art
Sub-threshold LSIs utilizing the sub-threshold region operation of MOSFETs attract attention in order to actualize LSIs of ultralow consumption power. However, since this design method is in the initial stage of development, there is a strong demand for the establishment of a design technology of an ultralow power consumption circuit. Up to now, various types of research have been conducted to actualize ultralow power LSIs (See, for example, a Non-Patent Document 1).
A differential amplifier circuit is a basic analog component circuit and is a component circuit of high versatility to achieve various analog operation functions. An operational amplifier, which is a differential amplifier circuit, is used in a negative feedback configuration and operates in a manner that two input terminals are virtually grounded. In general, the characteristics of an operational amplifier are determined by its bias current.
FIG. 1 is a block diagram showing a basic configuration of a prior art operational amplifier circuit of an open loop configuration. In the operational amplifier circuit of FIG. 1, an operational amplifier 1 operates with a bias current from a bias current source circuit 2. Therefore, in order to achieve low power characteristics of an operational amplifier circuit, it is feasible to reduce the bias current and make the circuit perform a minute current operation in, for example, the sub-threshold region. However, the operational amplifier circuit of ultralow power operation has had such a problem that its response time was increased due to the collapse of the virtual grounding caused by an input change ascribed to deterioration in the driving capability due to a minute current bias.
Prior art documents related to the present invention are as follows:    Patent Document 1: Japanese patent laid-open publication No. JP 2010-239554 A; and    Patent Document 2: Japanese patent laid-open publication No. JP 2011-182188 A.    Non-Patent Document 1: T. Hirose et al., “A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities”, Proceedings of the 36th European Solid-state Circuits Conference, pp. 114-117, September 2010; and    Non-Patent Document 2: M. Degrauwe et al., “Adaptive biasing CMOS amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 17, pp. 522-528, June 1982.
In order to solve the aforementioned problems, an ultralow power CMOS operational amplifier using the adaptive bias technology is proposed (See, for example, the Non-Patent Document 2). The adaptive bias technology is useful for operational amplifier design using a minute current. However, there is the problem of difficulty in generating a large adaptive bias current in the proposed system, which leads to a failure in making the operational amplifier have high speed.